With advances of semiconductor process technology and decreasing of process node, critical dimensions (CDs) of semiconductor devices are further reduced and channel widths of field-effect transistors (FETs) keep narrowing down. This may result in narrow channel effect to cause reduction of drive current of the FETs. Multi-gate devices such as Fin FETs are conventionally used to increase the channel width and thus to increase the drive current. However, the fabrication process of such multi-gate devices is complex and with high cost.
In a conventional integrated circuit (IC) fabrication process, shallow trench isolation (STI) structures are widely used as lateral isolation structures between semiconductor devices. FIG. 1 is a schematic illustrating a conventional STI structure. As shown, the fabrication process of the conventional STI structure 20 includes forming shallow trenches in a semiconductor substrate 10 by a dry etch process to isolate active regions in the semiconductor substrate, and forming a dielectric material layer inside the shallow trenches to completely fill the shallow trenches and cover the surface of the semiconductor substrate 10. The dielectric material layer is made of silicon oxide. The dielectric material layer may be planarized by a chemical mechanical polishing (CMP) technique to form the shallow trench structure 20.
FIG. 2 is a schematic illustrating a top view of the semiconductor substrate 10 after forming a transistor between STI structures. The transistor includes a gate 30 and source/drain 31 positioned on each side of the gate 30. The channel width of the transistor is shown as width D1 of the semiconductor substrate 10 under the gate 30.
As integration degree of the ICs is increasingly enhanced, the width D1 of the semiconductor substrate between neighboring STI structures or the channel width of the transistor decreases. The decrease of the channel width may cause reduction of the drive current of the transistor.